Advancements in Microprocessor Design: The Development of Minisys SoC
As the embedded systems and information technology sectors continue to thrive, the design of microprocessors has gained significant traction. Numerous universities and research institutions across China are now engaged in microprocessor design initiatives. However, many of these designs tend to be simplistic, characterized by basic hardware structures that often lack comprehensive support systems, including assemblers, compilers, operating systems, and various input/output interface circuits. This limitation results in a narrow range of applications and inefficient use of design resources due to the varying formats of instruction sets among these microprocessors.
In response to these challenges, our objective is to create a robust, high-performance embedded System on Chip (SoC) to streamline design efforts, enhance microprocessor education in higher education, and attract talent to the field of high-performance microprocessor development. Additionally, we aim to provide a free SoC soft core that can be utilized for cost-effective industrial control applications.
System Overview and Technical Specifications
The Minisys project is a 32-bit RISC-based SoC developed by the System Structure Laboratory at a prominent university's School of Computer Science and Engineering. The Minisys architecture comprises a SoC chip, associated I/O controllers, and relevant system software, all centered around a 32-bit RISC processor. The system software features a BIOS that provides a system function call interface for upper-layer programming, a keyboard driver, and an assembler (compiler) specifically designed for Minisys.
The architecture of the Minisys CPU includes 32 general-purpose registers, a 32-bit data bus, and a 16-bit address bus. The I/O unit encompasses a 4-bit controller for 7-segment LED displays, a 4x4 keyboard controller, a 16-bit timer/counter, a 32-bit system timer, a 16-bit PWM controller, a watchdog circuit, and a simple UART for serial communication.
Minisys is built upon the MIPS instruction set, featuring 32-bit fixed-length instructions. It supports 31 commonly used fixed-point instructions while allowing for a flexible use of the 32 general-purpose registers, with five designated for specific functions.
The architecture employs a Harvard structure, integrating 4KB of ROM and 4KB of RAM, both byte-addressable but using 32-bit as the primary data unit for CPU interaction. The addressing scheme for I/O components is unified with memory access, enabling the same instruction format for both operations.
The internal control circuit manages two interrupt sources, INT0 and INT1, with INT0 receiving higher priority, thus facilitating interrupt nesting. While the system includes stack pointer registers for stack operations, it does not provide direct push and pop instructions; therefore, these operations must be handled through software, placing responsibility for atomicity on the programmer.
Design Methodology
The design of the Minisys SoC encompasses both hardware and software components. The hardware design includes the CPU architecture, interface components, and BIOS development, while the software design focuses on the assembler.
In the CPU design phase, key considerations include defining the instruction set, structuring the CPU, organizing the register set, and implementing various functional components. The CPU's internal architecture is divided into five fundamental units: fetch unit, decode unit, control unit, execution unit, and storage unit. A modular design approach was employed, allowing each unit to be developed independently before integrating them into a complete CPU.
Fetch Unit: This unit is responsible for retrieving instructions from program ROM, updating the program counter (PC), and managing PC modifications for jump instructions. The design utilizes pre-existing ROM macro blocks for efficiency.
Decode Unit: The decode unit prepares operands for instruction execution. It analyzes the Minisys instruction set, determining whether data resides in registers or is an immediate value, and manages the reading and writing of registers based on the decoded instruction.
Control Unit: Serving as the operational core of the CPU, the control unit generates various control signals based on combinations of operation codes, function codes, and predefined conventions. It utilizes a specific marking system to identify operand sources.
Execution Unit: This unit executes logical, arithmetic, and shift operations, as well as managing comparisons and assignments.
Storage Unit: The storage unit implements data RAM and facilitates read/write operations. Like the instruction ROM, the data RAM is constructed using macro modules, ensuring consistency in initialization file formats.
Conclusion and Future Directions
The design process of the Minisys SoC illustrates a comprehensive approach to microprocessor development, addressing existing limitations and paving the way for enhanced educational opportunities in microprocessor design. By providing a modular, high-performance embedded system, we aim to reduce redundancy in design efforts and foster innovation in the field of microprocessor technology. As we continue to refine and expand the capabilities of the Minisys SoC, we hope to contribute significantly to the advancement of embedded systems and attract a new generation of engineers and developers to this dynamic field.
